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CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
Features

Functional Description
The CY7C12461KV18, CY7C12571KV18, CY7C12481KV18, and CY7C12501KV18 are 1.8V Synchronous Pipelined SRAMs equipped with DDR II+ architecture. The DDR II+ consists of an SRAM core with advanced synchronous peripheral circuitry. Addresses for read and write are latched on alternate rising edges of the input (K) clock. Write data is registered on the rising edges of both K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 8-bit words (CY7C12461KV18), 9-bit words (CY7C12571KV18), 18-bit words (CY7C12481KV18), or 36-bit words (CY7C12501KV18) that burst sequentially into or out of the device. Asynchronous inputs include an output impedance matching input (ZQ). Synchronous data outputs (Q, sharing the same physical pins as the data inputs D) are tightly matched to the two output echo clocks CQ/CQ, eliminating the need for separately capturing data from each individual DDR SRAM in the system design. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. These devices are down bonded from the 65nm 72M QDRII+/DDRII+ devices and hence have the same IDD/ISB1 values and the same JTAG ID code as the equivalent 72M device options. For details refer to the application note AN53189, 65nm Technology InterimQDRII+/DDRII+ SRAM device family description. Table 1. Selection Guide Description Max Operating Frequency Max Operating Current 450 400 375 333 MHz MHz MHz MHz Unit 450 x8 630 x9 630 x18 650 x36 820 400 580 580 590 750 375 550 550 570 710 333 510 510 520 640 MHz mA
36-Mbit Density (4M x 8, 4M x 9, 2M x 18, 1M x 36) 450 MHz Clock for High Bandwidth 2-word Burst for reducing Address Bus Frequency Double Data Rate (DDR) Interfaces (data transferred at 900 MHz) at 450 MHz Available in 2.0 Clock Cycle Latency Two Input Clocks (K and K) for precise DDR Timing SRAM uses rising edges only Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Systems Data Valid Pin (QVLD) to indicate Valid Data on the Output Synchronous Internally Self Timed Writes DDR II+ operates with 2.0 Cycle Read Latency when DOFF is asserted HIGH Operates similar to DDR I Device with 1 Cycle Read Latency when DOFF is asserted LOW Core VDD = 1.8V 0.1V; I/O VDDQ = 1.4V to VDD[1] Supports both 1.5V and 1.8V I/O supply HSTL Inputs and Variable Drive HSTL Output Buffers Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm) Offered in both Pb-free and non Pb-free Packages JTAG 1149.1 Compatible Test Access Port Phase Locked Loop (PLL) for Accurate Data Placement

Configurations
With Read Cycle Latency of 2.0 cycles: CY7C12461KV18 - 4M x 8 CY7C12571KV18 - 4M x 9 CY7C12481KV18 - 2M x 18 CY7C12501KV18 - 1M x 36
Note 1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4V to VDD.
Cypress Semiconductor Corporation Document Number: 001-53194 Rev. *I
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 31, 2011
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CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18
Logic Block Diagram (CY7C12461KV18)
A(20:0) LD K K DOFF
21
Write Add. Decode
Read Add. Decode
Address Register
Write Reg 2M x 8 Array
Write Reg
8
2M x 8 Array
CLK Gen.
Output Logic Control
R/W
Read Data Reg. 16 Control Logic CQ CQ 8 8 DQ[7:0] QVLD
VREF R/W NWS[1:0]
8 8
Reg. Reg.
Reg. 8
Logic Block Diagram (CY7C12571KV18)
A(20:0) LD K K DOFF
21
Write Add. Decode
Read Add. Decode
Address Register
Write Reg 2M x 9 Array
Write Reg
9
2M x 9 Array
CLK Gen.
Output Logic Control
R/W
Read Data Reg. 18 Control Logic CQ CQ 9 9 DQ[8:0] QVLD
VREF R/W BWS[0]
9 9
Reg. Reg.
Reg. 9
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CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18
Logic Block Diagram (CY7C12481KV18)
A(19:0) LD K K DOFF
20
Write Add. Decode
Read Add. Decode
Address Register
Write Reg 1M x 18 Array
Write Reg
18
1M x 18 Array
CLK Gen.
Output Logic Control
R/W
Read Data Reg. 36 Control Logic CQ CQ
18
VREF R/W BWS[1:0]
18 18
Reg. Reg.
Reg. 18 18
DQ[17:0] QVLD
Logic Block Diagram (CY7C12501KV18)
A(18:0) LD K K DOFF
19
Write Add. Decode
Read Add. Decode
Address Register
Write Reg 512K x 36 Array
Write Reg 512K x 36 Array
36
CLK Gen.
Output Logic Control
R/W
Read Data Reg. 72 Control Logic CQ CQ
36
VREF R/W BWS[3:0]
36 36
Reg. Reg.
Reg. 36 36
DQ[35:0] QVLD
Document Number: 001-53194 Rev. *I
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CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18
Contents
Pin Configuration ............................................................. 5 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout .................. 5 Functional Overview ........................................................ 9 Read Operations ......................................................... 9 Write Operations ......................................................... 9 Byte Write Operations ................................................. 9 DDR Operation ............................................................ 9 Depth Expansion ......................................................... 9 Programmable Impedance .......................................... 9 Echo Clocks ................................................................ 9 Valid Data Indicator (QVLD) ...................................... 10 PLL ............................................................................ 10 Application Example ...................................................... 10 IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13 Disabling the JTAG Feature ...................................... 13 Test Access Port--Test Clock ................................... 13 Test Mode Select (TMS) ........................................... 13 Test Data-In (TDI) ..................................................... 13 Test Data-Out (TDO) ................................................. 13 Performing a TAP Reset ........................................... 13 TAP Registers ........................................................... 13 TAP Instruction Set ................................................... 13 TAP Electrical Characteristics ...................................... 16 TAP AC Switching Characteristics ............................... 17 TAP Timing and Test Conditions .................................. 17 Power Up Sequence in DDR II+ SRAM ......................... 20 Power Up Sequence ................................................. 20 PLL Constraints ......................................................... 20 Maximum Ratings ........................................................... 21 Operating Range ............................................................ 21 Neutron Soft Error Immunity ......................................... 21 Electrical Characteristics .............................................. 21 DC Electrical Characteristics ..................................... 21 AC Electrical Characteristics ..................................... 22 Capacitance .................................................................... 23 Thermal Resistance ....................................................... 23 Switching Characteristics ............................................. 24 Switching Waveforms .................................................... 25 Read/Write/Deselect Sequence ................................ 25 Ordering Information ..................................................... 26 Ordering Code Definitions ......................................... 26 Package Diagram ........................................................... 27 Document History Page ................................................. 28 Sales, Solutions, and Legal Information ...................... 29 Worldwide Sales and Design Support ....................... 29 Products .................................................................... 29 PSoC Solutions ......................................................... 29
Document Number: 001-53194 Rev. *I
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CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18
Pin Configuration
The pin configuration for CY7C12461KV18, CY7C12571KV18, CY7C12481KV18, and CY7C12501KV18 follow.[2]
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C12461KV18 (4M x 8) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M NC NC NC NC NC NC VREF NC NC DQ6 NC NC NC TCK 3 A NC NC NC DQ4 NC DQ5 VDDQ NC NC NC NC NC DQ7 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NWS1 NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A QVLD NC 7 NC/144M NWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC NC NC NC NC NC VREF DQ1 NC NC NC NC NC TMS 11 CQ DQ3 NC NC DQ2 NC NC ZQ NC NC DQ0 NC NC NC TDI
CY7C12571KV18 (4M x 9) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M NC NC NC NC NC NC VREF NC NC DQ6 NC NC NC TCK 3 A NC NC NC DQ4 NC DQ5 VDDQ NC NC NC NC NC DQ7 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NC NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A QVLD NC 7 NC/144M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC NC NC NC NC NC VREF DQ1 NC NC NC NC NC TMS 11 CQ DQ3 NC NC DQ2 NC NC ZQ NC NC DQ0 NC NC DQ8 TDI
Note 2. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-53194 Rev. *I
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CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18
Pin Configuration
(continued)
The pin configuration for CY7C12461KV18, CY7C12571KV18, CY7C12481KV18, and CY7C12501KV18 follow.[2]
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C12481KV18 (2M x 18) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M DQ9 NC NC NC DQ12 NC VREF NC NC DQ15 NC NC NC TCK 3 A NC NC DQ10 DQ11 NC DQ13 VDDQ NC DQ14 NC NC DQ16 DQ17 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS1 NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A QVLD NC 7 NC/144M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 A NC DQ7 NC NC NC NC VREF DQ4 NC NC DQ1 NC NC TMS 11 CQ DQ8 NC NC DQ6 DQ5 NC ZQ NC DQ3 DQ2 NC NC DQ0 TDI
CY7C12501KV18 (1M x 36) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/144M DQ27 NC DQ29 NC DQ30 DQ31 VREF NC NC DQ33 NC DQ35 NC TCK 3 A DQ18 DQ28 DQ19 DQ20 DQ21 DQ22 VDDQ DQ32 DQ23 DQ24 DQ34 DQ25 DQ26 A 4 R/W A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS2 BWS3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A QVLD NC 7 BWS1 BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 LD A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC/72M NC DQ17 NC DQ15 NC NC VREF DQ13 DQ12 NC DQ11 NC DQ9 TMS 11 CQ DQ8 DQ7 DQ16 DQ6 DQ5 DQ14 ZQ DQ4 DQ3 DQ2 DQ1 DQ10 DQ0 TDI
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CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18
Table 2. Pin Definitions Pin Name DQ[x:0] I/O Pin Description
Input Output- Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write Synchronous operations. These pins drive out the requested data when the read operation is active. Valid data is driven out on the rising edge of both the K and K clocks during read operations. When read access is deselected, Q[x:0] are automatically tristated. CY7C12461KV18 DQ[7:0] CY7C12571KV18 DQ[8:0] CY7C12481KV18 DQ[17:0] CY7C12501KV18 DQ[35:0] InputSynchronous Load. Sampled on the rising edge of the K clock. This input is brought LOW when a bus Synchronous cycle sequence is defined. This definition includes address and read/write direction. All transactions operate on a burst of 2 data. LD must meet the setup and hold times around edge of K. InputNibble Write Select 0, 1 Active LOW (CY7C12461KV18 only). Sampled on the rising edge of the K Synchronous and K clocks during write operations. Used to select which nibble is written into the device during the current portion of the write operations. Nibbles not written remain unaltered. NWS0 controls D[3:0] and NWS1 controls D[7:4]. All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select ignores the corresponding nibble of data and it is not written into the device. InputByte Write Select 0, 1, 2, and 3 Active LOW. Sampled on the rising edge of the K and K clocks during Synchronous write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C12571KV18 BWS0 controls D[8:0] CY7C12481KV18 BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C12501KV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select ignores the corresponding byte of data and it is not written into the device. InputAddress Inputs. Sampled on the rising edge of the K clock during active read and write operations. These Synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C12461KV18 and 4M x 9 (2 arrays each of 2M x9) for CY7C12571KV18, 2M x 18 (2 arrays each of 1M x 18) for CY7C12481KV18, and 1M x 36 (2 arrays each of 512K x 36) for CY7C12501KV18. InputSynchronous Read or Write Input. When LD is LOW, this input designates the access type (read when Synchronous R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times around edge of K. Valid output indicator Input Clock Input Clock Echo Clock Echo Clock Input Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous data being presented to the device and to drive out data through Q[x:0]. Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock (K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 24. Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock (K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 24. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
LD
NWS0, NWS1
BWS0, BWS1, BWS2, BWS3
A
R/W
QVLD K K CQ CQ ZQ
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CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18
Table 2. Pin Definitions (continued) Pin Name DOFF I/O Input Pin Description PLL Turn Off Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin can be connected to a pull up through a 10 K or less pull up resistor. The device behaves in DDR I mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with DDR I timing. TDO for JTAG. TCK Pin for JTAG. TDI Pin for JTAG. TMS Pin for JTAG. Not Connected to the Die. Can be tied to any voltage level. Not Connected to the Die. Can be tied to any voltage level. Not Connected to the Die. Can be tied to any voltage level. Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC measurement points. Ground for the Device.
TDO TCK TDI TMS NC NC/144M NC/288M VREF VDD VSS VDDQ
Output Input Input Input N/A Input Input InputReference Ground
Power Supply Power supply Inputs to the Core of the Device. Power Supply Power Supply Inputs for the Outputs of the Device.
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CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18
Functional Overview
The CY7C12461KV18, CY7C12571KV18, CY7C12481KV18, and CY7C12501KV18 are synchronous pipelined Burst SRAMs equipped with a DDR interface, which operates with a read latency of two cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to VSS the device behaves in DDR I mode with a read latency of one clock cycle. Accesses are initiated on the rising edge of the positive input clock (K). All synchronous input and output timing is referenced from the rising edge of the input clocks (K and K). All synchronous data inputs (D[x:0]) pass through input registers controlled by the rising edge of the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the input clocks (K and K). All synchronous control (R/W, LD, NWS[X:0], BWS[X:0]) inputs pass through input registers controlled by the rising edge of the input clock (K). CY7C12481KV18 is described in the following sections. The same basic descriptions apply to CY7C12461KV18, CY7C12571KV18, and CY7C12501KV18.
Byte Write Operations
Byte write operations are supported by the CY7C12481KV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the Byte Write Select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read, modify, or write operations to a byte write operation.
DDR Operation
The CY7C12481KV18 enables high performance operation through high clock frequencies (achieved through pipelining) and DDR mode of operation. The CY7C12481KV18 requires two No Operation (NOP) cycle during transition from a read to a write cycle. At higher frequencies, some applications require third NOP cycle to avoid contention. If a read occurs after a write cycle, address and data for the write are stored in registers. The write information is stored because the SRAM cannot perform the last word write to the array without conflicting with the read. The data stays in this register until the next write cycle occurs. On the first write cycle after the read(s), the stored data from the earlier write is written into the SRAM array. This is called a Posted write. If a read is performed on the same address on which a write is performed in the previous cycle, the SRAM reads out the most current data. The SRAM does this by bypassing the memory array and reading the data from the registers.
Read Operations
The CY7C12481KV18 is organized internally as two arrays of 1M x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting R/W HIGH and LD LOW at the rising edge of the positive input clock (K). The address presented to the address inputs is stored in the read address register. Following the next two K clock rise, the corresponding 18-bit word of data from this address location is driven onto the Q[17:0] using K as the output timing reference. On the subsequent rising edge of K, the next 18-bit data word is driven onto the Q[17:0]. The requested data is valid 0.45 ns from the rising edge of the input clock (K and K). To maintain the internal logic, each read access must be allowed to complete. Read accesses can be initiated on every rising edge of the positive input clock (K). When read access is deselected, the CY7C12481KV18 first completes the pending read transactions. Synchronous internal circuitry automatically tristates the output following the next rising edge of the positive input clock (K). This enables a transition between devices without the insertion of wait states in a depth expanded memory.
Depth Expansion
Depth expansion requires replicating the LD control signal for each bank. All other control signals can be common between banks as appropriate.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to enable the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between 175 and 350, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature.
Write Operations
Write operations are initiated by asserting R/W LOW and LD LOW at the rising edge of the positive input clock (K). The address presented to address inputs is stored in the write address register. On the following K clock rise, the data presented to D[17:0] is latched and stored into the 18-bit write data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock (K) the information presented to D[17:0] is also stored into the write data register, provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. Write accesses can be initiated on every rising edge of the positive input clock (K). Doing so pipelines the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K). When the write access is deselected, the device ignores all inputs after the pending write operations have been completed.
Echo Clocks
Echo clocks are provided on the DDR II+ to simplify data capture on high speed systems. Two echo clocks are generated by the DDR II+. CQ is referenced with respect to K and CQ is referenced with respect to K. These are free running clocks and are synchronized to the input clock of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 24.
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CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18
Valid Data Indicator (QVLD)
QVLD is provided on the DDR II+ to simplify data capture on high speed systems. The QVLD is generated by the DDR II+ device along with data output. This signal is also edge aligned with the echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives. of stable clock. The PLL can also be reset by slowing or stopping the input clock K and K for a minimum of 30 ns. However, it is not necessary to reset the PLL to lock to the desired frequency. The PLL automatically locks 20 s after a stable clock is presented. The PLL may be disabled by applying ground to the DOFF pin. When the PLL is turned off, the device behaves in DDR I mode (with one cycle latency and a longer access time). For information, refer to the application note, PLL Considerations in QDRII/DDRII/QDRII+/DDRII+.
PLL
These chips use a PLL that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the PLL is locked after 20 s
Application Example
Figure 1 shows two DDR II+ used in an application. Figure 1. Application Example
DQ A
SRAM#1
LD R/W BWS
ZQ CQ/CQ KK
R = 250ohms DQ A
SRAM#2
LD R/W BWS
ZQ CQ/CQ KK
R = 250ohms
DQ Addresses BUS LD MASTER R/W (CPU or ASIC) BWS Source CLK Source CLK Echo Clock1/Echo Clock1 Echo Clock2/Echo Clock2
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CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18
Table 3. Truth Table The truth table for the CY7C12461KV18, CY7C12571KV18, CY7C12481KV18, and CY7C12501KV18 follow.[3, 4, 5, 6, 7, 8] Operation Write Cycle: Load address; wait one cycle; input write data on consecutive K and K rising edges. Read Cycle: (2.0 cycle Latency) Load address; wait two cycles; read data on consecutive K and K rising edges. NOP: No Operation Standby: Clock Stopped K L-H LD L R/W L DQ D(A) at K(t + 1) DQ D(A+1) at K(t + 1)
L-H
L
H
Q(A) at K(t + 2)
Q(A+1) at K(t + 2)
L-H Stopped
H X
X X
High Z Previous State
High Z Previous State
Table 4. Write Cycle Descriptions The write cycle description table for CY7C12461KV18 and CY7C12481KV18 follows.[3, 9] BWS0/ BWS1/ NWS0 L NWS1 L K L-H K - Comments During the data portion of a write sequence CY7C12461KV18 both nibbles (D[7:0]) are written into the device. CY7C12481KV18 both bytes (D[17:0]) are written into the device.
L
L
-
L-H During the data portion of a write sequence CY7C12461KV18 both nibbles (D[7:0]) are written into the device. CY7C12481KV18 both bytes (D[17:0]) are written into the device. - During the data portion of a write sequence CY7C12461KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C12481KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L
H
L-H
L
H
-
L-H During the data portion of a write sequence CY7C12461KV18 only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered. CY7C12481KV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. - During the data portion of a write sequence CY7C12461KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C12481KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
H
L
L-H
H
L
-
L-H During the data portion of a write sequence CY7C12461KV18 only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered. CY7C12481KV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. - No data is written into the devices during this portion of a write operation. L-H No data is written into the devices during this portion of a write operation.
H H
H H
L-H -
Notes 3. X = "Don't Care," H = Logic HIGH, L = Logic LOW, represents rising edge. 4. Device powers up deselected with the outputs in a tristate condition. 5. "A" represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst. 6. "t" represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the "t" clock cycle. 7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well. 8. Ensure that when clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 9. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved.
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Table 5. Write Cycle Descriptions The write cycle description table for CY7C12571KV18 follows.[3, 9] BWS0 L L H H K L-H - L-H - K - L-H - L-H Comments During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. During the data portion of a write sequence, the single byte (D[8:0]) is written into the device. No data is written into the device during this portion of a write operation. No data is written into the device during this portion of a write operation.
Table 6. Write Cycle Descriptions The write cycle description table for CY7C12501KV18 follows.[3, 9] BWS0 L L L L H H H H H H H H BWS1 L L H H L L H H H H H H BWS2 L L H H H H L L H H H H BWS3 L L H H H H H H L L H H K L-H - L-H - L-H - L-H - L-H - L-H - K - Comments During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device.
L-H During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. - During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered.
L-H During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. - During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered.
L-H During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. - During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered.
L-H During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. - During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered.
L-H During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. - No data is written into the device during this portion of a write operation. L-H No data is written into the device during this portion of a write operation.
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IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V I/O logic levels. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in TAP Controller Block Diagram on page 16. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to enable fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This enables shifting of data through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several No Connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and output ring. The Boundary Scan Order on page 19 shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 18.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull up resistor. TDO must be left unconnected. Upon power up, the device comes up in a reset state, which does not interfere with the operation of the device.
Test Access Port--Test Clock
The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see the TAP Controller State Diagram on page 15. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the registers. The output is active, depending upon the current state of the TAP state machine (see Instruction Codes on page 18). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This Reset does not affect the operation of the SRAM and can be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a High Z state.
TAP Instruction Set
Eight different instructions are possible with the three-bit instruction register. All combinations are listed in Instruction Codes on page 18. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in this section in detail. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK.
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IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test-Logic-Reset state. SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High Z state until the next command is supplied during the Update IR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured in the boundary scan register. The TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift-DR controller state. EXTEST OUTPUT BUS TRISTATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tristate mode. The boundary scan register has a special bit located at bit #108. When this scan cell, called the "extest output bus tristate," is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
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The state diagram for the TAP controller follows.[10] Figure 2. TAP Controller State Diagram
1
TEST-LOGIC RESET 0 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 1 0 0 1 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 0 0 1 0
0
TEST-LOGIC/ IDLE
1
SELECT DR-SCAN 0 1
1
Note 10. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
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Figure 3. TAP Controller Block Diagram
0 Bypass Register 2 TDI Selection Circuitry 31 Instruction Register 30 29 . . 2 1 0 1 0 Selection Circuitry TDO
Identification Register 108 . . . . 2 1 0
Boundary Scan Register
TCK TMS TAP Controller
TAP Electrical Characteristics
Over the Operating Range[11, 12, 13] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input and Output Load Current GND VI VDD Test Conditions IOH =2.0 mA IOH =100 A IOL = 2.0 mA IOL = 100 A -0.3 -5 Min 1.4 1.6 0.4 0.2 0.65VDD VDD + 0.3 0.35VDD 5 Max Unit V V V V V V A
Notes 11. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table. 12. Overshoot: VIH(AC) < VDDQ + 0.3V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3V (Pulse width less than tCYC/2). 13. All Voltage referenced to Ground.
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TAP AC Switching Characteristics
Over the Operating Range[14, 15] Parameter tTCYC tTF tTH tTL Setup Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH Output Times tTDOV tTDOX TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 10 ns ns TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 ns ns ns TMS Setup to TCK Clock Rise TDI Setup to TCK Clock Rise Capture Setup to TCK Rise 5 5 5 ns ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH TCK Clock LOW 20 20 Description Min 50 20 Max Unit ns MHz ns ns
TAP Timing and Test Conditions
Figure 4 shows the TAP timing and test conditions.[15] Figure 4. TAP Timing and Test Conditions
0.9V 50 TDO Z0 = 50 CL = 20 pF
ALL INPUT PULSES 1.8V 0.9V 0V
(a)
GND
tTH
tTL
Test Clock TCK
tTMSS tTMSH
tTCYC
Test Mode Select TMS
tTDIS tTDIH
Test Data In TDI
Test Data Out TDO
tTDOV tTDOX
Notes 14. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 15. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
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Table 7. Identification Register Definitions Instruction Field Revision Number (31:29) Value CY7C12461KV18 000 CY7C12571KV18 000 CY7C12481KV18 000 CY7C12501KV18 000 Description Version number.
Cypress Device ID 11010111100000100 11010111100001100 11010111100010100 11010111100100100 Defines the type of (28:12) SRAM. Cypress JEDEC ID (11:1) ID Register Presence (0) 00000110100 00000110100 00000110100 00000110100 Allows unique identification of SRAM vendor. Indicates the presence of an ID register.
1
1
1
1
Table 8. Scan Register Sizes Register Name Instruction Bypass ID Boundary Scan Table 9. Instruction Codes Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures the input and output ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the input and output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High Z state. Do Not Use: This instruction is reserved for future use. Captures the input and output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Bit Size 3 1 32 109
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Table 10. Boundary Scan Order Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Bump ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H Bit # 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Bump ID 10G 9G 11F 11G 9F 10F 11E 10E 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A 8B 7C 6C 8A 7A 7B 6B Bit # 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 Bump ID 6A 5B 5A 4A 5C 4B 3A 2A 1A 2B 3B 1C 1B 3D 3C 1D 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1H Bit # 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Bump ID 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R Internal
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Power Up Sequence in DDR II+ SRAM
DDR II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
PLL Constraints

PLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var. The PLL functions at frequencies down to 120 MHz. If the input clock is unstable and the PLL is enabled, then the PLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 20 s of stable clock to relock to the desired clock frequency.
Power Up Sequence
Apply power and drive DOFF either HIGH or LOW (All other inputs can be HIGH or LOW). Apply VDD before VDDQ. Apply VDDQ before VREF or at the same time as VREF. Drive DOFF HIGH. Provide stable DOFF (HIGH), power and clock (K, K) for 20 s to lock the PLL.
Figure 5. Power Up Waveforms
K K
~ ~
Unstable Clock
> 20 s Stable clock
~ ~
Start Normal Operation
Clock Start (Clock Starts after V DD / V DDQ Stable)
VDD / VDDQ
DOFF
V DD / V DDQ Stable (< +/- 0.1V DC per 50ns ) Fix HIGH (or tie to VDDQ)
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Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ............................... -65 C to +150 C Ambient Temperature with Power Applied -55 C to +125 C Supply Voltage on VDD Relative to GND ........-0.5V to +2.9V Supply Voltage on VDDQ Relative to GND.......-0.5V to +VDD DC Applied to Outputs in High-Z ......... -0.5V to VDDQ + 0.3V DC Input Voltage[12]............................... -0.5V to VDD + 0.3V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V Latch up Current..................................................... >200 mA SEL LMBU
Neutron Soft Error Immunity
Parameter LSBU Description Logical Single-Bit Upsets Logical Multi-Bit Upsets Single Event Latchup Test Conditions 25 C 25 C Typ 197 0 Max* Unit 216 0.01 FIT/ Mb FIT/ Mb FIT/ Dev
85 C
0
0.1
Operating Range
Range Commercial Industrial Ambient Temperature (TA) 0 C to +70 C -40 C to +85 C VDD[16] 1.8 0.1V VDDQ[16] 1.4V to VDD
* No LMBU or SEL events occurred during testing; this column represents a statistical 2, 95% confidence limit calculation. For more details refer to Application Note AN 54908 "Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates"
Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range[13] Parameter VDD VDDQ VOH VOL VOH(LOW) VOL(LOW) VIH VIL IX IOZ VREF Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current GND VI VDDQ GND VI VDDQ, Output Disabled Note 17 Note 18 IOH =0.1 mA, Nominal Impedance IOL = 0.1 mA, Nominal Impedance Test Conditions Min 1.7 1.4 VDDQ/2 - 0.12 VDDQ/2 - 0.12 VDDQ - 0.2 VSS VREF + 0.1 -0.15 2 2 0.68 0.75 Typ 1.8 1.5 Max 1.9 VDD VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2 VDDQ + 0.15 VREF - 0.1 2 2 0.95 Unit V V V V V V V V A A V
Input Reference Voltage[19] Typical Value = 0.75V
Notes 16. Power up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 17. Outputs are impedance controlled. IOH = -(VDDQ/2)/(RQ/5) for values of 175 < RQ < 350. 18. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 < RQ < 350. 19. VREF(min) = 0.68V or 0.46VDDQ, whichever is larger, VREF(max) = 0.95V or 0.54VDDQ, whichever is smaller.
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Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range[13] Parameter IDD[20] Description VDD Operating Supply Test Conditions VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC 450 MHz (x8) (x9) (x18) (x36) 400 MHz (x8) (x9) (x18) (x36) 375 MHz (x8) (x9) (x18) (x36) 333 MHz (x8) (x9) (x18) (x36) ISB1 Automatic Power down Current Max VDD, Both Ports Deselected, VIN VIH or VIN VIL f = fMAX = 1/tCYC, Inputs Static 450 MHz (x8) (x9) (x18) (x36) 400 MHz (x8) (x9) (x18) (x36) 375 MHz (x8) (x9) (x18) (x36) 333 MHz (x8) (x9) (x18) (x36) Min Typ Max 630 630 650 820 580 580 590 750 550 550 570 710 510 510 520 640 340 340 340 340 320 320 320 320 310 310 310 310 290 290 290 290 mA mA mA mA mA mA mA Unit mA (continued)
AC Electrical Characteristics
Over the Operating Range [12] Parameter VIH VIL Description Input HIGH Voltage Input LOW Voltage Test Conditions Min VREF + 0.2 -0.24 Typ - - Max VDDQ + 0.24 VREF - 0.2 Unit V V
Note 20. The operation current is calculated with 50% read cycle and 50% write cycle.
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Capacitance
Tested initially and after any design or process change that may affect these parameters. Parameter CIN CO Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V Max 4 4 Unit pF pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 165 FBGA Package 13.7 3.73 Unit C/W C/W
Figure 6. AC Test Loads and Waveforms
VREF = 0.75V VREF OUTPUT Device Under Test Z0 = 50 RL = 50 VREF = 0.75V 0.75V VREF OUTPUT Device Under Test ZQ 5 pF 0.25V Slew Rate = 2 V/ns 0.75V R = 50 ALL INPUT PULSES 1.25V 0.75V
[21]
ZQ
(a)
RQ = 250
INCLUDING JIG AND SCOPE
RQ = 250 (b)
Note 21. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms.
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Switching Characteristics
Over the Operating Range [21, 22] Cypress Consortium Parameter Parameter tPOWER tCYC tKH tKL tKHKH tKHKH tKHKL tKLKH tKHKH Description VDD(Typical) to the First Access[23] K Clock Cycle Time Input Clock (K/K) HIGH Input Clock (K/K) LOW K Clock Rise to K Clock Rise (rising edge to rising edge) 450 MHz 400 MHz 375 MHz 333 MHz Min Max Min Max Min Max Min Max 1 2.20 0.4 0.4 0.94 - 8.4 - - - 1 2.50 0.4 0.4 1.06 - 8.4 - - - 1 2.66 0.4 0.4 1.13 - 8.4 - - - 1 3.0 0.4 0.4 1.28 - 8.4 - - - Unit ms ns ns ns ns
Setup Times tAVKH tSA tSC tIVKH tSCDDR tIVKH tSD tDVKH Hold Times tHA tKHAX tHC tKHIX tHCDDR tKHIX tHD tKHDX Output Times tCO tCHQV tDOH tCHQX tCCQO tCQOH tCQD tCQDOH tCQH tCQHCQH tCHZ tCLZ tCHCQV tCHCQX tCQHQV tCQHQX tCQHCQL tCQHCQH tCHQZ
Address Setup to K Clock Rise 0.275 Control Setup to K Clock Rise (LD, R/W) 0.275 Double Data Rate Control Setup to Clock (K/K) 0.22 Rise (BWS0, BWS1, BWS2, BWS3) D[X:0] Setup to Clock (K/K) Rise 0.22 Address Hold after K Clock Rise Control Hold after K Clock Rise (LD, R/W) Double Data Rate Control Hold after Clock (K/K) Rise (BWS0, BWS1, BWS2, BWS3) D[X:0] Hold after Clock (K/K) Rise K/K Clock Rise to Data Valid Data Output Hold after Output K/K Clock Rise (Active to Active) K/K Clock Rise to Echo Clock Valid Echo Clock Hold after K/K Clock Rise Echo Clock High to Data Valid Echo Clock High to Data Invalid Output Clock (CQ/CQ) HIGH[24] CQ Clock Rise to CQ Clock Rise (rising edge to rising edge)[24] Clock (K/K) Rise to High-Z (Active to High-Z)[25, 26] Clock (K/K) Rise to Low-Z[25, 26] Echo Clock High to QVLD Valid[27] Clock Phase Jitter PLL Lock Time (K) K Static to PLL Reset[28] 0.275 0.275 0.22 0.22
- - - - - - - -
0.4 0.4 0.28 0.28 0.4 0.4 0.28 0.28
- - - - - - - -
0.4 0.4 0.28 0.28 0.4 0.4 0.28 0.28
- - - - - - - -
0.4 0.4 0.28 0.28 0.4 0.4 0.28 0.28
- - - - - - - -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ns
- 0.45 - 0.45 - 0.45 - 0.45 -0.45 - -0.45 - -0.45 - -0.45 - - 0.45 - 0.45 - 0.45 - 0.45 -0.45 - -0.45 - -0.45 - -0.45 - - 0.15 - 0.20 - 0.20 - 0.20 -0.15 - -0.20 - -0.20 - -0.20 - 0.85 - 1.00 - 1.08 - 1.25 - 0.85 - 1.00 - 1.08 - 1.25 - - 0.45 - 0.45 - 0.45 - 0.45
tCHQX1 tQVLD tCQHQVLD PLL Timing tKC Var tKC Var tKC lock tKC lock tKC Reset tKC Reset
-0.45 - -0.45 - -0.45 - -0.45 - -0.15 0.15 -0.20 0.20 -0.20 0.20 -0.20 0.20 - 20 30 0.15 - - - 20 30 0.20 - - - 20 30 0.20 - - - 20 30 0.20 - -
Notes 22. When a part with a maximum frequency above 333 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and outputs data with the output timings of that frequency range. 23. This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD min initially before a read or write operation can be initiated. 24. These parameters are extrapolated from the input timing parameters (tCYC/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by design and are not tested in production. 25. tCHZ, tCLZ are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured 100 mV from steady-state voltage. 26. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO. 27. tQVLD specification is applicable for both rising and falling edges of QVLD signal. 28. Hold to >VIH or Document Number: 001-53194 Rev. *I
Page 24 of 29
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CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18
Switching Waveforms
Read/Write/Deselect Sequence [29, 30, 31, 32]
Figure 7. Waveform for 2.0 Cycle Read Latency
NOP 1
K t KH K t KL
READ 2
READ 3
NOP 4
NOP 5
NOP 6
WRITE 7
WRITE 8
READ 9
NOP 10
NOP 11
12
tCYC
t KHKH
LD tSC tHC R/W A A0 t SA t HA QVLD A1 A2 A3 A4
tQVLD
t QVLD
t QVLD
t HD tSD tSD D20 D21 t CHZ t CQD t CQDOH D30 D31 Q40 Q41 tHD
DQ t (Read Latency = 2.0 Cycles) t CQOH CQ CLZ
Q00
Q01 Q10 t DOH
Q11
tCO t CCQO
t CQOH CQ
t CCQO
t CQH
t CQHCQH
DON'T CARE
UNDEFINED
Notes 29. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1. 30. Outputs are disabled (High-Z) one clock cycle after a NOP. 31. The third NOP cycle between read to write transition is not necessary for correct device operation when Read Latency = 2.0 cycles; however at high frequency operation, it is required to avoid bus contention. 32. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 001-53194 Rev. *I
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CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18
Ordering Information
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Table 11. Ordering Information Speed (MHz) 400 Ordering Code CY7C12481KV18-400BZC CY7C12501KV18-400BZC Package Diagram Package Type Operating Range Commercial
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Ordering Code Definitions
CY 7C 12XXX K V18 - 400 BZ C Temperature Range: C = Commercial Package Type: BZ = 165-ball FPBGA Frequency Range: 400 MHz Voltage: 1.8 V 65 nm Die Revision Part Identifier: 12XXX = 12481 or 12501 = 36-Mbit DDR-II+ SRAM 2-Word Burst Architectur Marketing Code: 7C = SRAM Company ID: CY = Cypress
Document Number: 001-53194 Rev. *I
Page 26 of 29
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CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18
Package Diagram
Figure 8. 165-ball FBGA (13 x 15 x 1.4 mm), 51-85180
TOP VIEW BOTTOM VIEW PIN 1 CORNER PIN 1 CORNER O0.08
1 A B 11 C A D B E F 10 9 8 7 6 5 4 2 3 4 5 6 7 8 9 10 11
MC MCAB
-0.06 +0.14 3
O0.25 O0.50
(165X)
2 1
1.00
C D
15.000.10
G E H J F
15.000.10
G
K L M
14.00
H J K
N P R
7.00
L M N
A
P R
A 5.00 B 13.000.10 10.00
1.00
1.40 MAX.
0.530.05
0.25 C
B 0.15 C 0.15(4X)
13.000.10
0.36
SEATING PLANE C
NOTES : SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD) PACKAGE WEIGHT : 0.475g JEDEC REFERENCE : MO-216 / ISSUE E PACKAGE CODE : BB0AC
51-85180 *C
Document Number: 001-53194 Rev. *I
Page 27 of 29
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CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18
Document History Page
Document Title: CY7C12461KV18/CY7C12571KV18/CY7C12481KV18/CY7C12501KV18, 36-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Document Number: 001-53194 REV. ** *A ECN NO. 2702761 2747707 Orig. of Change VKN/PYRS VKN/AESA Submission Description Of Change Date 05/06/2009 08/03/2009 New Data Sheet Converted from preliminary to final For 450 MHz speed, changed tCO, tCCQO, tCHZ from 370 ps to 450 ps and tDOH, tCQOH, tCLZ from -370 ps to -450 ps Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information Post to external web Updated Input and Output Capacitance. Modified Ordering code disclaimer. Included CY7C12481KV18-400BZC in the Ordering Information table Updated 165-ball package diagram. Included "CY7C12501KV18-450BZXC" part in the Ordering Information table. Included "CY7C12481KV18-400BZXC" part in the Ordering Information table. Removed CY7C12501KV18-450BZXC from the Ordering Information table. Included CY7C12501KV18-450BZXC part to the Ordering Information table. Added Ordering Code Definition. Updated Ordering Information and added Ordering Code Definitions.
*B *C *D *E *F *G *H *I
2761928 2762555 2868256 2877876 2890573 2896003 3056557 3158296
AJU NJY VKN VKN VKN NJY NJY AJU
09/10/2009 09/11/2009 01/28/2010 02/12/2010 03/11/2010 03/19/2010 12/10/2010 01/31/2011
Document Number: 001-53194 Rev. *I
Page 28 of 29
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CY7C12461KV18, CY7C12571KV18 CY7C12481KV18, CY7C12501KV18
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
Products
Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
(c) Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-53194 Rev. *I
Revised January 31, 2011
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QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.
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